Integrated circuits (IC) include various semiconductor devices formed within or on layers of dielectric material that overlay a substrate. The devices formed in or on the dielectric layers may include MRS transistors, bipolar transistors, diodes, and diffused resistors. Other devices formed in or on the dielectric material may include thin film resistors and capacitors. Metal lines interconnect the semiconductor devices to power the devices and enable the devices to share and exchange information. Interconnects may extend horizontally between devices within a dielectric layer as well as vertically between dielectric layers. These metal lines are connected to each other by a series of interconnects. The electrical interconnects or metal lines are first patterned into the dielectric layers to form vertical and horizontal recessed features (vias and trenches) that are subsequently filled with metal. The resulting layer containing metal-filled lines residing in a dielectric is referred to as a metallization layer.
A long-standing objective in the advancement of IC technology has been the scaling down of IC dimensions. Scaling-down of IC dimensions is critical to obtaining higher speed performance of ICs. An increase in IC performance is normally accompanied by a decrease in device area and/or an increase in device density. An increase in device density results in a decrease in via and trench dimensions (widths) used to form interconnects. However, as feature dimensions on wafers decrease, negative consequences may occur. For example, reduced-size features may result in less reliable interconnects.
Copper interconnects are typically used in ICs. However, drawbacks of copper interconnects in small features include performance as a result of, for example, voids formed during deposition, electromigration tendencies of copper, line resistance, and via resistance. Therefore, there exists a need for the integration of copper and non-copper interconnects, the metal for a feature being selected depending on the size of the feature. Embodiments of the present disclosure are directed to an integration scheme for Cu and other metal interconnects to solve these and other problems.